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700mhz, differential-to-3.3v lvpecl zero delay clock generator ics8735-21 idt? / ics? 3.3v lvpecl zero delay clock generator 1 ics8735am-21 rev. a july 31, 2008 general description the ics8735-21 is a highly versatile 1:1 differential- to-3.3v lvpecl clock generator and a member of the hiperclocks? family of high performance clock solutions from idt. the clk, nclk pair can accept most standard differential input levels. the ics8735-21 has a fully integrated pll and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25mhz to 700mhz. t he reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1: 8. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clocks. the pll_sel pin can be used to bypass the pll for system test and debug purposes. in bypass mode, the reference clock is routed around the pll and into the internal output dividers. features ? one differential 3.3v lvpecl output pair one differential feedback output pair ? differential clk/nclk input pair ? clk/nclk pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? output frequency range: 31.25mhz to 700mhz ? input frequency range: 31.25mhz to 700mhz ? vco range: 250mhz to 700mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 ? cycle-to-cycle jitter: 25ps (maximum) ? static phase offset: 50ps 100ps ? full 3.3v supply voltage ? 0c to 70c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 sel0 sel1 nc nc clk nclk nc mr v cco nc q nq qfb nqfb nc v cco v cc nc nfb_in fb_in sel2 v ee nc nc v cc pll_se l v cca sel3 v ee nc nc nc block diagram pll_sel clk nclk fb_in nfb_in sel0 sel1 sel2 sel3 mr q nq qfb nqfb pll 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 0 1 1, 2, 4, 8, 16, 32 , 64 pullup pullup pulldown pullup pulldown pullup pulldown pulldown pulldown pulldown pulldown pulldown pin assignments 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 nqfb v ee sel2 fb_in nfb_in v cc mr nclk clk qfb nc sel1 sel0 v cc pll_sel v cca sel3 v cco q nq ics8735-21 20-lead soic 7.5mm x 12.8mm x 2.3mm package body m package top view ics8735-21 32-lead vfqfn 5mm x 5mm x 0.925mm package body k package top view
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 2 ics8735am-21 rev. a july 31, 2008 table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics name type description clk input pulldown non-inverting differential clock input. nclk input pullup inverting differential clock input. nfb_in input pullup inverting differential feedback input to phase detector for regenerating clocks with ?zero delay.? fb_in input pulldown non-inverted differential feedba ck input to phase detector for regenerating clocks with ?zero delay.? mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true output q to go low and the inverted output nq to go high. when logic low, the internal dividers and the outputs are enabled . lvcmos / lvttl interface levels. sel0, sel1, sel2, sel3 input pulldown determines output divider values in table 3. lvcmos / lvttl interface levels. pll_sel input pullup pll select. selects between the pll and reference clock as the input to the dividers. when low, selects re ference clock. when high, selects pll. lvcmos/lvttl interface levels. nq, q output differential output pair. lvpecl interface levels. nqfb, qfb output different ial feedback output pair. lvpecl interface levels. v ee power negative supply pin. v cc power core supply pins. v cca power analog supply pin. v cco power output supply pin. symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 3 ics8735am-21 rev. a july 31, 2008 function tables table 3a. control input function table *note: vco frequency range for all conf igurations above is 250mhz to 700mhz. inputs outputs pll_sel = 1 pll enable mode sel3 sel2 sel1 sel0 reference frequency range (mhz)* q/nq, qfb/nqfb 0000 250 - 700 1 0001 125 - 350 1 0010 62.5 - 175 1 0011 31.25 - 87.5 1 0100 250 - 700 2 0101 125 - 350 2 0110 62.5 - 175 2 0111 250 - 700 4 1000 125 - 350 4 1001 250 - 700 8 1010 125 - 350 x2 1011 62.5 - 175 x2 1100 31.25 - 87.5 x2 1101 62.5 - 175 x4 1110 31.25 - 87.5 x4 1111 31.25 - 87.5 x8
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 4 ics8735am-21 rev. a july 31, 2008 table 3b. pll bypass function table inputs outputs pll_sel = 0 pll bypass mode sel3 sel2 sel1 sel0 q /nq, qfb/nqfb 0z000 4 0001 4 0010 4 0011 8 0100 8 0101 8 0110 16 0111 16 1000 32 1001 64 1010 2 1011 2 1100 4 1101 1 1110 2 1111 1
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 5 ics8735am-21 rev. a july 31, 2008 absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c table 4b. lvcmos/lvttl dc characteristics, v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c item rating supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5v outputs, i o continuos current surge current 50ma 100ma package thermal impedance, ja 20 lead soic 32 lead vfqfn 46.2 c/w (0 lfpm) 37.0 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v v cco output supply voltage 3.135 3.3 3.465 v i ee power supply current 150 ma i cca analog supply current 15 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v cc + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current sel[0:3], mr v cc = v in = 3.465v 150 a pll_sel v cc = v in = 3.465v 5 a i il input low current sel[0:3], mr v cc = 3.465v, v in = 0v -5 a pll_sel v cc = 3.465v, v in = 0v -150 a
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 6 ics8735am-21 rev. a july 31, 2008 table 4c. differential dc characteristics, v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4d. lvpecl dc characteristics, v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: outputs terminated with 50 ? to v cco ? 2v. table 5. input frequency characteristics, v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, fb_in v cc = v in = 3.465v 150 a nclk, nfb_in v cc = v in = 3.465v 5 a i il input low current clk, fb_in v cc = 3.465v, v in = 0v -5 a nclk, nfb_in v cc = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input vo ltage; note 1, 2 v ee + 0.5 v cc ? 0.85 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco ? 1.4 v cco ? 0.9 v v ol output low voltage; note 1 v cco ? 2.0 v cco ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v symbol parameter test conditio ns minimum typical maximum units f in input frequency clk, nclk pll_sel = 1 31.25 700 mhz pll_sel = 0 700 mhz
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 7 ics8735am-21 rev. a july 31, 2008 ac electrical characteristics table 6. ac characteristics, v cc = v cca = v cco = 3.3v 5%, v ee = 0v, t a = 0c to 70c note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output diffe rential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as the time difference between the input reference clock and the averaged feedback input signal across all cond itions, when the pll is locked and the input reference frequency is stable. note 5: characterized at vco frequency of 622mhz. note 6: phase jitter is dependent on the input source used. parameter symbol test conditio ns minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 pll_sel = 0v, f 700mhz 3.0 4.2 ns t sk(o) output skew; note 2, 3 pll_sel = 0v 20 ps t sk(?) static phase offset; note 3, 4 pll_sel = 3.3v -50 50 150 ps t jit(cc) cycle-to-cycle jitter; note 3, 5 25 ps t jit( ) phase jitter; note 3, 5, 6 50 ps t l pll lock time 1ms t r / t f output rise/fall time; note 7 20% to 80% @ 50mhz 300 700 ps odc output duty cycle 47 53 %
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 8 ics8735am-21 rev. a july 31, 2008 parameter measureme nt information 3.3v output load ac test circuit phase jitter and static phase offset cycle-to-cycle jitter differential input level output skew output rise/fall time scope qx nqx lvpecl v ee 2v 1.3v 0.165v v cc, v cca, v cco nclk clk nfb_in fb_in ? ? (?) v oh v ol v oh v ol ? ? ? ? cycle n t cycle n+1 t jit(cc) = | t cycle n ? t cycle n+1 | 1000 cycles nq, nqfb q, qfb v cc v ee v cmr cross points v pp nclk clk nqx qx nqy qy t sk(o) clock outputs 20% 80% 80% 20% t r t f v swing
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 9 ics8735am-21 rev. a july 31, 2008 parameter measurement in formation, continued output duty cycle/pulse width/period propagation delay application information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. fb_in/nfb_in inputs for applications not requiring the use of the differential input, both fb_in and nfb_in can be left floa ting. though not required, but for additional protection, a 1k ? resistor can be tied from fb_in to ground. outputs: lvpecl outputs all unused lvpecl outputs can be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. t pw t period t pw t period odc = x 100% nq, nqfb q, qfb t pd nclk clk nq, nqfb q, qfb
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 10 ics8735am-21 rev. a july 31, 2008 power supply filtering technique as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perform- ance, power supply isolation is required. the ics8735-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc, v cca and v cco should be individually connected to the power supply plane through vias, and 0.01f bypass capacitors should be used for each pin. figure 1 illustrates this for a generic v cc pin and also shows that v cca requires that an additional 10 ? resistor along with a 10 f bypass capacitor be connected to the v cca pin. the 10 ? resistor can also be replaced by a ferrite bead. figure 1. power supply filtering wiring the differential input to accept single ended levels figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possib le to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input vo ltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 2. single-ended signal driving differential input v cc v cca 3.3v 10 ? 10f .01f .01f v_ref single ended clock input v cc clk nclk r1 1k c1 0.1u r2 1k
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 11 ics8735am-21 rev. a july 31, 2008 differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 3a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 3a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 3b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 3d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 3f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 12 ics8735am-21 rev. a july 31, 2008 termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impeda nce follower outputs that generate ecl/lvpecl compatible ou tputs. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 4a and 4b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 4a. 3.3v lvpecl output termination figure 4b. 3.3v lvpecl output termination v cc - 2v 50 ? 50 ? rtt z o = 50 ? z o = 50 ? fout fin rtt = z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v 125 ? 125 ? 84 ? 84 ? z o = 50 ? z o = 50 ? fout fin
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 13 ics8735am-21 rev. a july 31, 2008 schematic example figure 5 shows a schematic example of the ics8735-21. in this example, the input is driven by an hcsl driver. the zero delay buffer is configured to operate at 155.52mhz input and 77.75mhz output. the logic control pins are configured as follows: sel [3:0] = 0101; pll_sel = 1 the decoupling capacitors should be physically located near the power pin. for ics8735-21. figure 5. ics8735- 21 lvpecl buffer schematic example r7 10 3.3v sp = space (i.e. not intstalled) zo = 50 ohm ru3 1k sel3 vcc sel1 c1 0.1uf bypass capacitors located near the power pins r8 50 vcca sel3 c11 0.01u vcca r1 50 vcc (155.5 mhz) vcc sel[3:0] = 0101, divide by 2 vcc sel0 ru7 sp c2 0.1uf sel2 vcc sel0 sel2 rd6 sp (77.75 mhz) rd7 1k r9 50 (u1-4) vcc ru4 1k r6 50 rd4 sp zo = 50 ohm zo = 50 ohm r4 50 ru5 sp lvpecl_input + - (u1-13) pll_sel r5 50 (u1-17) hcsl r2 50 sel1 zo = 50 ohm rd3 sp u1 ics8735-21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 19 18 17 clk nclk mr vcci nfb_in fb_in sel2 vee nqfb qfb nq q vcco sel3 vcca pll_sel nc sel1 sel0 vcci c3 0.1uf vcc=3.3v r3 50 rd5 1k c16 10u ru6 1k pll_sel
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 14 ics8735am-21 rev. a july 31, 2008 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 6. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of am kor?s thermally/electrically enhance leadfame base package, amkor technology. figure 6. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 15 ics8735am-21 rev. a july 31, 2008 power considerations this section provides information on power dissipa tion and junction temperature for the ics8735-21. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8735-21 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i cc_max = 3.465v * 150ma = 519.8mw power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 2 * 30mw = 60mw total power_ max = (3.465v, with all outputs switching) = 519.8mw + 60mw = 579.8mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 83.2c/w per table 7a below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.580w * 83.2c/w = 118.3c. th is is well below the limit of 125c. this calculation is only an example. tj will obviously vary dependi ng on the number of loaded ou tputs, supply voltage, air flow and the type of board (single layer or multi-layer). table 7a. thermal resistance ja for 20 lead soic, forced convection table 7b. thermal resistance ja for 32 lead vfqfn, forced convection ja vs. air flow linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 16 ics8735am-21 rev. a july 31, 2008 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 7. figure 7. lvpecl driver circuit and termination t o calculate worst case power dissipation into the lo ad, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 17 ics8735am-21 rev. a july 31, 2008 reliability information table 8a. ja vs. air flow table for a 20 lead tssop table 8b. ja vs. air flow table for a 32 lead vfqfn, forced convection transistor count the transistor count for ics8735-21 is: 2969 package outline and package dimensions package outline - m suffix for 20 lead soic table 9a. package dimensions for 20 lead soic reference document: jedec pu blication 95, ms-013, ms-119 ja vs. air flow linear feet per minute 0200500 single-layer pcb, jedec standard te st boards 83.2c/w 65.7c/w 57.5c/w multi-layer pcb, jedec standard test boards 46.2c/w 39.7c/w 36.8c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 37.0c/w 32.4c/w 29.0c/w 300 millimeters all dimensions in millimeters symbol minimum maximum n 20 a 2.65 a1 0.10 a2 2.05 2.55 b 0.33 0.51 c 0.18 0.32 d 12.60 13.00 e 7.40 7.60 e 1.27 basic h 10.00 10.65 h 0.25 0.75 l 0.40 1.27 0 7
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 18 ics8735am-21 rev. a july 31, 2008 package outline - k suffix for 32 lead vfqfn the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 9b below. table 9b. package dimensions for 32 lead vfqfn reference document: jede c publication 95, mo-220 jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or
ics8735-21 700mhz, differential -to-3.3v lvpecl zero delay clock generator idt? / ics? 3.3v lvpecl zero delay clock generator 19 ics8735am-21 rev. a july 31, 2008 ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 8735am-21 ics8735am-21 20 lead soic tube 0 c to 70 c 8735am-21t ics8735am-21 20 lead soic 1000 tape & reel 0 c to 70 c 8735am-21lf ics8735am-21lf ?lead-free? 20 lead soic tube 0 c to 70 c 8735am-21lft ics8735am-21lf ?lead-free? 20 lead soic 1000 tape & reel 0 c to 70 c 8735AK-21LF ics8735a21l ?lead-free? 32 lead vfqfn tray 0 c to 70 c 8735AK-21LFt ics8735a21l ?lead-free? 32 lead vfqfn 2500 tape & reel 0 c to 70 c while the information presented herein has been checked for both a ccuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for use in normal commercial applications. any other applications, such as those requiring extended temperature ranges, high reliabilit y or other extraordinary environmental requirements are not recommended without additional processing by idt. idt rese rves the right to change any ci rcuitry or specifications with out notice. idt does not authorize or warrant any idt product for use in life support devi ces or critical medical instruments.
ics8735-21 700mhz, differential-to-3.3v lvpecl zero delay clock generator www.idt.com ? 2008 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800-345-7015 (inside usa) +408-284-8200 (outside usa) contact information: www.idt.com

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